1. Field of the Invention
The present invention relates to a process for flushing high-speed buffers in a serial link and a device for implementing the process. More specifically, the invention relates to a process and device for flushing the serial link buffers of an integrated circuit or two integrated circuits comprising a parallel-serial and serial-parallel port.
2. Description of Related Art
The invention is particularly applicable when it is desirable to use gigabit-speed serial links having an error rate that is non-null, for example on the order of 10.sup.-15 to 10.sup.-17, to produce an internal link to a logic unit which would normally be produced by a parallel link that is not prone to interference. This substitution is motivated by the fact that high-speed serial links have many advantages. For example, high-speed serial links provide high density and ease of connection with identical passbands, and allow a long link, for example up to ten meters, which is impossible with standard internal logical links.